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Highlights
- 8 fully discrete R-2R DA modules for combination into true symmetrical push/pull decoders.
- 4 groups of fully discrete, truly symmetrical native DSD decoders.
- Fully discrete, true symmetrical power transfer design.
- Two ultra-high frequency 90/98 MHz Accusilicon 318B femtosecond clocks ensure a synchronous clock for the entire unit without PLL up frequency.
- 32bit / PCM384K /DSD512 asynchronous transmission Amanero 384 uses the FPGA synchronous clock.
- The entire digital circuit built with 1 pc FPGA and 5 pc CPLD programmable chipsets to separate the different configured circuits for avoiding interruptions, data process in parallel mode.
- Supports firmware updates to improve sound quality.
- All digital process mode settings are accessible via buttons on the front panel (no need to open the case).
Firmware update port on the back (firmware update without opening the case).
Advantages and disadvantages of the R-2R DAC
Advantages
1. The R-2R does not convert the clock signal into the output signal.
2. R-2R is insensitive to jitter, while Delta-Sigma D/A is much more sensitive to jitter.
3. The output signal is much more precise compared to Delta-Sigma D/A.
Disadvantages
1. The distortion factor is extremely good today with sigma-delta chips; R2R conductors are also good, but not as good.
2. Interference and accuracy of conductor resistance are very difficult to avoid and require complex technology to correct them.
R-2R basic design on the market
The R-2R DAC is very popular these days and is available from DIY kits to high-end products.
At the lower end of the DIY market, R2R designs are often based on the old technology developed long ago by MSB, and only include the basic R2R ladder design, rather than the wonderful correction design of the original MSB technology. This design uses serial-mode data shift register logic chips to convert data into an analog signal. The structural problems of R2R technology cannot be avoided, and performance depends solely on the accuracy of the ladder resistances.
In the high-end market, the R2R design is much more complex and achieves the best performance. A simple R2R ladder is simply not sufficient to achieve good performance and sound quality! Some manufacturers use shift registers, a less complex and less powerful design based on traditional logic chips operating in serial mode, to correct the ladder.
A far better design switches resistors in parallel mode. An ultrafast FPGA controls and corrects the R2R ladder. The parallel design mode controls each bit at a time, achieving unprecedented performance. (In parallel mode, only one clock cycle is required to output all the data; serial design mode requires at least 8 to 24 clock cycles.) The parallel design is much more complicated. If designed correctly, it can correct every bit of the ladder. The photo below shows a design using such an FPGA, which can correct the inevitable imperfections of the R2R ladder caused by resistor tolerance and glitches to achieve the best performance.
Accuracy of conductor resistances (tolerance)
Many believe that the tolerance of the resistors in the ladder is the most important factor for achieving the best performance. Today, 24-bit resolution is standard. What tolerance is required to achieve 24-bit resolution?
At 16 bits, the tolerance of 1/66536, 0.1% (1/1000), is far from sufficient; even a tolerance of 0.01% (1/10000), the best tolerance available today, cannot correctly process 16-bit requests; we are not even counting 24 bits here!
Resistor tolerance will never resolve the imperfections of a conductor. This would require resistors with a tolerance of 0.00001% capable of handling 24-bit resolution. This is only theoretically possible, as discrete logic chips already have too high an internal impedance and would destroy the impossible tolerance of a resistor.
The solution is to correct the conductors and not rely solely on the tolerance of resistors. It's a combination of both: Ultra-low tolerance resistors controlled by a correction technology using a very fast FPGA are applicable in our design.
The importance of the FPGA/CPLD
FPGA stands for Programmable Array Logic. Nowadays, FPGAs are used in many high-quality DACs, such as the popular ROCKNA WAVEDREAM DAC.
We have been using the FPGA in our DAC products since 2008.
The R-7 has 1 pc FPGA and 5 pc CPLD programmable chipsets built in to separate the different configured circuits and avoid interruptions.
The internal hardware design is completely controlled by complex software. A major advantage is the fact that the software in the FPGA can be easily upgraded to offer new features or improve performance. This type of design is very flexible and future-proof!
FPGA/CPLD tasks
1. The FPGA high-performance SPDIF interface replaces traditional SPDIF interface chips such as DIR9001, WM8805 or AK411X, which have lower performance compared to the FPGA.
2. Complete reclocking process with FIFO design for all inputs. This ensures that the output data is fully synchronized with the clock signal to eliminate any jitter.
3. Built-in 2X, 4X, and 8X oversampling and digital filters, plus four different NOS modes (analog 6dB filtering only), so you can configure it to your liking!
4. Built-in special design to simulate the TDA1541A + SAA7220 sound.
Specifications
| S/N ratio | >110 dB |
Output impedance | <10 ohms (RCA/XLR) |
| Output Level | 2.5V (RCA) 5V (XLR) 2MA+2MA (ACSS) |
| Frequency Response | 20Hz - 20KHz (< - 0.5dB) |
THD+N | <0.01% |
| Input Sensitivity |
|
Support Operate Systems (USB) | Windows, OSX, Linux, ISO |
| Support Sampling | USB & IIS: 44.1kHz - 384 kHz /32-bit DSD64-512 Coaxial mode: 44.1kHz - 192kHz Optical mode: 44.1kHz - 96kHz |
| Power requirement | version 1: 100-120V AC 50/60 Hz Version 2: 220-240V AC 50/60 Hz |
| Power Consumption | 19W |
| Package Weight | Approximately 5KG |
Dimensions | W240 X L360 X H80 (MM, fully aluminum) |
| Accessories | AC power cord X1 USB cable X1 |
