Audio GD R1 - Fully Discrete R2R DAC

Delivery time on request.
(All devices are handmade to customer order)

Highlights

• 8 fully discrete R-2R DA modules for combination to true symmetrical push/pull decoders.
• 4 groups of full discrete true symmetric native DSD decoders.
• Fully discrete true symmetrical power transmission design.
• 2pcs ultra high frequency 90/98MHz Accusilicon 318B femtosecond clocks provide synchronous clock for the whole unit without PLL up frequency.
• 32bit / PCM384K /DSD512 asynchronous transmission Amanero 384 use the FPGA synchronous clock.
• The whole digital circuit built with 1 pc FPGA and 5 pc CPLD programmable chipsets to separate the different configured circuits for avoiding interruption, data process in parallel mode.
• Support firmware updates to improve sound quality.
• All digital process mode settings are accessible via buttons on the front (no need to open the case).
  Firmware update port on the back (firmware update without opening the case).

Pros and cons of the R-2R DAC

Benefits

1. the R-2R does not convert the clock signal into the output signal.

2. R-2R is insensitive to jitter, while delta-sigma D/A is much more sensitive to jitter.

3. The output signal is much more precise compared to Delta-Sigma D/A.

Disadvantages

1. The distortion factor is extremely good with Sigma-Delta chips today; R2R ladders are also good, but not as good.

2. Interference and accuracy of the ladder resistances are very difficult to avoid and require complex technology to fix them.

R-2R base design on the market

R-2R DAC is very popular nowadays and available from DIY kits to high-end products.

At the low end of the DIY market, the R-2R design is often based on the old technology developed by MSB long ago, and includes only the basic R2R conductor design, not the wonderful corrective design of the original ones MSB technology. This design uses serial mode data shift register logic chips to convert the data to an analog signal. The structural problems of R2R technology cannot be avoided, and performance depends solely on the accuracy of the conductor resistances.

In the high-end market, the R2R design is much more complex and achieves the best performance. A simple R2R ladder is simply not sufficient to achieve good performance and sound quality! Some manufacturers use shift registers. A less complex and less powerful design based on traditional logic chips operating in series mode to correct the ladder.

A far better design switches resistors in parallel mode. An ultra-fast FPGA controls and corrects the R2R ladder. Parallel design mode controls each bit at a time for unprecedented performance. (Parallel mode only takes 1 clock cycle to output all data; serial design mode needs at least 8 to 24 clock cycles) Parallel design is much more complicated. If properly designed, it can correct every bit of the ladder. The photo below shows a design with such an FPGA that can correct the inevitable imperfections of the R2R ladders caused by the tolerance of the resistors and glitches to get the best performance.


Accuracy of conductor resistances (tolerance)

Many believe that the tolerance of the resistances in the conductor is most important to achieve the best performance.Today, 24-bit resolution is standard. What tolerance is required to achieve 24-bit resolution?
At 16-bit, the tolerance of 1/66536, 0.1% (1/1000) is far from sufficient , even a tolerance of 0.01% (1/10000), the best tolerance available today, cannot handle 16-bit requests correctly; we don't even expect 24 bits here!

The tolerance of resistance will never solve the imperfections of a conductor. This would require resistors with a tolerance of 0.00001% that can handle 24-bit resolution. This is only theoretically possible since the discrete switching logic chips already have too high an internal impedance and would destroy the impossible tolerance of a resistor.

The solution is to correct the ladder and not just rely on the tolerance of resistors. It is a combination of both: Ultra-low tolerance resistors controlled by correction technology with a very fast FPGA are applicable in our design.


The importance of the FPGA/CPLD
FPGA stands for Programmable Array Logic. Nowadays FPGAs are used in many high quality DACs, such as the popular ROCKNA WAVEDREAM DAC.
We have been using the FPGA in our DAC products since 2008.
The R-7 built in 1 pc FPGA and 5 pc CPLD programmable chipsets to separate the different configured circuits and avoid breaks.

The internal hardware design is fully controlled by complex software. A major benefit is the fact that the software in the FPGA can be easily upgraded to offer new features or improve performance. Such a design is very flexible and future-proof!
　

FPGA/CPLD tasks

1. The FPGA high-performance SPDIF interface replaces traditional SPDIF interface chips such as DIR9001, WM8805 or AK411X which has lower performance compared to FPGA.

2. Full re-clocking process with FIFO design for all inputs. In this way, the output data is fully synchronized with the clock signal to avoid any jitter.

3. Built-in 2X, 4X and 8X oversampling and digital filters and moreover 4 different NOS modes (only analog 6dB filtering) . So you can configure it according to your taste!

4. Built-in special design to simulate TDA1541A + SAA7220 sound.

Specifications