Audio-GD R-29 - Headphone Amplifier / Preamplifier and R-2R DAC

Delivery time approx. 2 weeks

Fully discrete transistor headphone amplifier/preamplifier and R-2R DAC in one model. Integrated multi-OS and NOS modes. Support for PCM384 and DSD512

The difference from the R-28 MK3

The R-28 MK3 is a fully symmetrical headphone amplifier/preamplifier with discrete transistors and an R-2R DAC in one model.

The R-29 is a fully discrete headphone amplifier/preamplifier with transistors and an R-2R DAC in one model.

R-29 Features

1. Fully symmetrical headphone amplifier/preamplifier with discrete transistors and DAC in one model, the maximum output power of the headphone amplifier reaches 3800 mW, making it suitable for most headphones.

2. The device has two gain modes: 12 dB low gain for headphones with sensitivity over 95 dB and 22 dB high gain combined with strong power sufficient to drive the HE6 with about 85 dB sensitivity. If the customer wants a gain of 6-12 dB, the total gain is 28-34 dB.

3. Built-in 5 linear power supplies and two pure Class-A power supplies

4. Built-in 2 groups of fully discrete true DSD-native decoders and 4 groups of fully discrete R-2R PCM decoders and 32 Bit / PCM384K / DSD512 asynchronous transfer Amanero 384.

5. USB transmits the IIS signal to the FPGA processor and receives the clock signal from the FPGA processor. The USB interface has no built-in data clocks, the signal transmission is very accurate, and the sound quality is significantly improved.

6. The FPGA processes data in parallel mode. The IIS data is transmitted in serial transmission mode, each data transmission requires one clock cycle, a data frame (including L and R data) requires 64 clock cycles for processing or transmission, so the data is affected by the 64 clock cycles.

However, the parallel data processing and transmission mode requires only one clock cycle to complete the processing and transmission of a data frame, thus avoiding the influence of clock stability.

The IIS input (including USB and HDMI IIS) is combined into double 32-bit parallel data after input, the SPDIF input is combined into double 24-bit parallel data after the decoder, and the DSD input is combined into double 64-bit parallel data after input.

The parallel processing and transmission mode can improve sound quality in terms of transparency and detail, but remains analog.

Advantages and disadvantages of R-2R DACs

Advantages

1. R-2R does not convert the clock signal into the output signal.

2. R-2R is insensitive to jitter. Delta-Sigma D/A converters are much more sensitive to jitter.

3. The output signal is significantly more precise compared to Delta-Sigma D/A converters.

Disadvantages

1. THD is very good today with Sigma-Delta chips compared to R2R ladders, but not as good.

2. Disturbances and inaccuracies of ladder resistors are very difficult to avoid and require complex technologies to fix them.

Basic design of R-2R on the market

The R-2R DAC is very popular nowadays and is available from DIY kits to fully high-end products. 

In the lower segment of the DIY market, the R-2R design is often based on an old technology developed long ago by MSB and only includes the basic R2R ladder design, without the wonderful correction design of the original MSB technology.

This design uses data shift register logic chips in serial mode to convert data into an analog signal. The structural problems of R2R technology cannot be avoided, and performance depends solely on the accuracy of the ladder resistors. 

In the high-end market, the R2R design is much more complex and achieves better performance. A simple R2R ladder is simply not enough to achieve good performance and high sound quality! Some manufacturers use a shift register design. A less complex and less efficient design based on traditional logic chips operating in serial mode to correct the ladder.

A far better design switches resistors in parallel mode. An ultra-fast FPGA controls and corrects the R2R ladder. The parallel mode controls each bit individually, achieving unprecedented performance. (In parallel mode, only one clock cycle is needed to output all data; in serial mode, at least 8 to 24 clock cycles are required.)

The parallel design is much more complicated. Once properly designed, it can correct every bit of the ladder. The photo below shows a design with such an FPGA that can correct the inevitable imperfections of the R2R ladder caused by the intolerance of resistor disturbances and achieve the best performance.

Accuracy of ladder resistors (tolerance)

Many people believe that the tolerance of the resistors in the ladder is the most important for achieving the best performance. Nowadays, a resolution of 24 bits is standard. What tolerance is required to achieve a resolution of 24 bits?

Looking at 16 bits, a tolerance of 1/66536, 0.1% (1/1000) is far from sufficient, even a tolerance of 0.01% (1/10000), currently the best available tolerance worldwide, cannot correctly process 16 bits; here we are not even calculating 24 bits!

The tolerance of the resistor will never solve the imperfections of a ladder. This would require resistors with a tolerance of 0.00001% and the ability to process a resolution of 24 bits. However, this is only theoretically possible, as the discreteness of the switching logic chips already has too high an internal impedance and negates the impossible tolerance of a resistor.

The solution is to correct the traces and not rely on resistor tolerance. It is a combination of both: resistors with extremely low tolerance controlled by a correction technology, and very fast FPGAs used in our design.

Meaning of FPGA/CPLD

FPGA stands for "Field Programmable Gate Array." 
Nowadays, FPGA is used in many high-quality DACs, such as the popular ROCKNA WAVEDREAM DAC. We have been using FPGA in our DAC products since 2008.

The R-29 features an integrated FPGA and three CPLD programmable chipsets to separate the various configured circuits and avoid interruptions.

The internal hardware design is fully controlled by complex software. A major advantage is that the software in the FPGA can be easily updated to offer new features or improve performance. Such a design is very flexible and future-proof!

FPGA/CPLD tasks

1. The powerful FPGA SPDIF interface replaces conventional SPDIF interface chips like DIR9001, WM8805, or AK411X, which have lower performance compared to the FPGA.

2. Complete re-clocking process with FIFO design, applicable to all inputs. This way, the output data remains fully synchronized with the clock signal to avoid any jitter.

3. Integrated 2X, 4X, and 8X oversampling and digital filters as well as 4 different true NOS modes (analog 6-dB filtering only). This allows you to configure the device exactly to your preferences!

4. Integrated special design to simulate the sound of vinyl records.

Built-in excellent, true discrete amplifier

The final signal stage is the analog output stages, which have a decisive influence on the ultimate sound quality of the DAC. 

After the D/A conversion by the R2R D/A modules, the analog signal is carried through fully discrete, matched transistor output stages

The special high-speed ACSS output stages are feedback-free and current-driven. 

They are so special because almost all other designs have to convert the signal multiple times from current to voltage and back, which leads to less detail and a less defined soundstage.

The output stages feature two pairs of 15-W transistors that provide strong driver power. The diamond differential design prevents switching distortion, operates in Class A, but does not draw high current at idle. The balance drive mode suppresses noise and distortion and improves the soundstage, background, and transparency, etc.

High-performance power supply design

In total, 5 groups of ultra-fast and extremely low-noise power supplies ensure a very clean power supply for the digital parts of the DAC. For the analog amplifiers, two groups of pure Class-A power supplies are installed, which make the sound more transparent and analog.

Technical details